The present invention relates to the field of programmable devices. Programmable devices, such as FPGAs, typically includes thousands of programmable logic cells that use combinations of logic gates and/or look-up tables to perform logic operations. Programmable devices also include a number of functional blocks having specialized logic devices adapted to specific logic operations, such as adders, multiply and accumulate circuits, phase-locked loops, and one or more memory units for storage and retrieval of data used by the logic cells. The logic cells and functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
The configuration of the logic cells, functional blocks, switching circuit, and other components of the programmable device is referred to as configuration data. Configuration data can be stored in volatile or non-volatile memory on the programmable device. Additionally, configuration data can be provided and temporarily or permanently loaded into the programmable device during its manufacturing. Users specify a user design that performs a desired information processing function. Compilation software tools analyze the user design and generate corresponding configuration data that implements the desired information processing function using a programmable device. The user-created configuration data can be temporarily or permenently loaded into one or more programmable devices to implement the user design. If the user design is changed, updated configuration data can be loaded into the programmable device to implement the changed user design.
Traditionally, memory blocks within a programmable device can exchange data with the logic cells at a rate of one bit per data line per clock cycle. For example, if the memory block is connected with logic cells via eight data lines (i.e. an eight bit data bus), then data is communicated at a rate of up to eight bits per clock cycle. This data communication scheme is commonly referred to as single data rate (SDR) communication.
There are several techniques for increasing the data communication rates between memory blocks and logic cells in programmable devices. The user can optimize the user design to allow for a higher clock frequency of the programmable device when implementing the user design. However, this is difficult or impossible for some user designs. Moreover, although this increases the rate at which data is communicated between logic cells and memory blocks, it also increases the rate at which logic cells can process data. Thus, increasing the clock frequency does not remedy situations in which logic cells can process data faster than it can be stored or retrieved from a memory block.
In some programmable devices, user designs can specify the width of the data bus between memory blocks and logic cells. For these types of programmable device, the data communication rate between a memory block and logic cells can be increased by increasing the width of data bus. This allows more bits of data to be stored or retrieved in parallel per clock cycle. However, the configurable switching circuit of the programmable device typically has a limited number of high speed connections and a larger number of slower connections. Increasing the width of the data bus requires the allocation of additional connections in the configurable switching circuit, often taking away high speed connections from other portions of the user design. In many cases, this increases signal delays on timing critical signal paths, which results in a decrease in the maximum operating speed of the user design.
It is therefore desirable for a programmable device to include memory blocks that provide improved data communication rates with logic cells. It is further desirable for memory blocks in a programmable device to provide improved data communication rates with logic cells without taking addition connection resources from the configurable switching circuit. It is further desirable for a programmable device to include two or more memory blocks operating at different data communication rates as needed. It is also desirable for a memory block to allow for different data communication rates at different times or on different memory ports as required. It is additionally desirable for a programmable device to enable any of its logic cells to communicate with memory blocks at an improved data rate as needed.